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IP Cores Product List

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Error Correction Code "Viterbi Decoder"

Error Correction Code "Viterbi Decoder"

Soft decision decoding / hard decision decoding, error correction codes that support both.

The "Viterbi Decoder" is an FPGA IP core for Viterbi decoding that corresponds to convolutional codes, which are widely used as representative error correction coding schemes. It supports both soft decision decoding and hard decision decoding. It is compatible with constraint length 7 (171 oct, 133 oct) convolutional codes, which are standard in many communication standards including IEEE802.11a. It can be applied to various applications. 【Features】 ■ Achieves a maximum line speed of approximately 110 Mbps and is adaptable to the IEEE802.11a standard ■ Built-in de-puncturing function ■ Supports coding rates of 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, and 7/8 ■ Implements a speed conversion block corresponding to the coding rate ■ Configuration that does not use memory blocks (EAB) ■ Allows setting of the traceback length via parameters ■ Configurable soft decision bit width *For more details, please refer to the PDF document or feel free to contact us.

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Error Correction Code "Reed-Solomon Express"

Error Correction Code "Reed-Solomon Express"

High-speed Reed-Solomon achieving a throughput of over 1 Gbps.

The "Lead Solomon Express" is an error correction encoding/decoding (Encoder/Decoder) IP core that achieves a throughput of over 1 Gbps by processing error location polynomials and error values in a pipeline manner. It supports variable data block lengths. 【Features】 ■ Achieves a throughput of over 1 Gbps ■ Supports variable data block lengths ■ The number of check bits, primitive polynomials, and generator polynomials can be customized according to your requirements. *For more details, please refer to the PDF document or feel free to contact us.

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NVMe IP core for FPGA

NVMe IP core for FPGA

Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.

The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Limited-time bit/sof files for various Xilinx/Intel FPGA boards are available, allowing performance evaluation on actual hardware before purchase.

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SATA IP core for FPGA

SATA IP core for FPGA

High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes SSD performance, enabling high-speed transfers of over 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual devices before purchase. Additionally, the core product comes with reference designs that operate on various Xilinx/Intel FPGA evaluation boards as standard, allowing development to start based on this reference design, enabling rapid product development.

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UDP 10G IP core for FPGA

UDP 10G IP core for FPGA

Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!

The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, so you can evaluate and test this core on actual hardware before purchasing.

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25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides a performance and bandwidth of 25G, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

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TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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Dynamic Neural Accelerator(DNA)

Dynamic Neural Accelerator(DNA)

Seamlessly accelerate increasingly complex compute-intensive AI workloads!

The "Dynamic Neural Accelerator (DNA)" is a flexible deep learning inference IP core characterized by high computational power, ultra-low latency, and a scalable inference engine. It boasts excellent power efficiency compared to other standard processors while achieving ultra-low latency for inference in streaming data. Please feel free to contact us if you have any inquiries. 【Features】 ■ Ultra-low latency AI inference IP core ■ Robust open-source MERA software framework ■ Compatible with both FPGA and ASIC/SoC (The photo and the link below show an example of DNA mounted on the Bittware (Molex Japan) FPGA card IA420F.) *For more details, please refer to the link below, download the PDF, or contact us. Reference link: https://www.bittware.com/ja/ip-solutions/edgecortix-dynamic-neural-accelerator/

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Error Correction Code "Reed-Solomon Encoder/Decoder"

Error Correction Code "Reed-Solomon Encoder/Decoder"

Error correction code with the capability to add bit/byte interleaving function.

The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding based on the Reed-Solomon method, used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, as well as the primitive polynomial and generator polynomial, can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.

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TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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TOE1G-IP core for FPGA

TOE1G-IP core for FPGA

TCP/IP communication functionality can be implemented with pure hardware logic without a CPU!

The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes with a reference design compatible with Xilinx/Altera FPGAs as a standard attachment to the core product, which can help shorten product development time.

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USB 3.0 IP core for FPGA

USB 3.0 IP core for FPGA

With the USB3.0 IP core, it is possible to develop a highly versatile FAT32 data recorder in a short period of time!

The 【USB3.0-IP】 complies with the USB3.0 standard Revision 1.0 and includes both the link layer and protocol layer, making it easy to implement a USB3.0 interface when combined with an external PHY chip from TI. A reference design compatible with Xilinx/Altera FPGAs is included as standard with the core product, which can help shorten product development time.

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TOE 40G IP core for FPGA

TOE 40G IP core for FPGA

Achieved 40 times speed 10GbE TCP/IP communication function with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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